Asiczen Releases its SMBus Verification IP

Asiczen Technologies announces the release of its UVM based SMBUS verification IP. azSMB is a UVM based verification component (UVC) that can be used by IP and SoC makers to test their System Management Bus (SMB) interface design effectively and quickly. This easy-to-use UVC can be easily integrated to any UVM based environment and can be used to generate a variety of scenario without much effort. The System Management Bus (abbreviated to SMBus or SMB) is a single-ended simple two-wire bus for the purpose of lightweight communication. Most commonly it is found in computer motherboards for communication with the power

Asiczen Releases its AHB Verification IP

Asiczen Technologies announces the release of its UVM based AHB verification IP. azAHB is fully compliant with AMBA 5 AHB specification. azAHB is a UVM based verification component (UVC) that can be used by IP and SoC makers to test their AHB interface design effectively and quickly. This easy-to-use UVC can be easily integrated to any UVM based environment and can be used to generate a variety of scenario without much effort. AHB is a bus protocol introduced in Advanced Microcontroller Bus Architecture. A simple transaction on the AHB consists of an address phase and a subsequent data phase. Access

Asiczen Releases its CAN Verification IP

Asiczen Technologies announces the release of its UVM based CAN verification IP. azCAN is fully compliant with CAN specification 2.0. azCAN is a UVM based verification component (UVC) that can be used by IP and SoC makers to test their CAN interface design effectively and quickly. This easy-to-use UVC can be easily integrated to any UVM based environment and can be used to generate a variety of scenario without much effort. CAN is a multi-master serial bus standard for connecting Electronic Control Units [ECUs] also known as nodes. Two or more nodes are required on the CAN network to communicate. The complexity of the node

Asiczen Releases its APB Verification IP

Asiczen Technologies announces the release of its UVM based APB verification IP. azAPB is fully compliant with AMBA APB specification. azAPB is a UVM based verification component (UVC) that can be used by IP and SoC makers to test their APB interface design effectively and quickly. This easy-to-use UVC can be easily integrated to any UVM based environment and can be used to generate a variety of scenario without much effort. APB is designed for low bandwidth control accesses, for example register interfaces on system peripherals. This bus has an address and data phase similar to AHB, but a much reduced, low complexity

Asiczen Releases its I2C and I2S Verification IP’s

Asiczen Technologies announces the release of its UVM based I2C and I2S verification IPs. These are additions to the series of low speed serial verification IPs that Asiczen offers. These VIPs conform to the latest specifications of their corresponding protocols and support all configurations. I2C is one of the most popular low speed interfaces used in SoCs for configuration and memory interfacing. I2S is used to connect audio devices together. More Details  

Asiczen Releases its SPI and UART Verification IP’s

Asiczen Technologies announces the release of its UVM based SPI and UART verification IPs. These are the first two in the series of low speed serial verification IPs that are in the pipeline. These VIPs conform to the latest specifications of their corresponding protocols and support all configurations. Serial Peripheral Interface (SPI) and Universal Asynchronous Receiver Transmitter(UART) are two of the most popular low speed interfaces used in SoCs for configuration and memory interfacing. More Details    

Asiczen Releases OCP Verification IP

Asiczen Technologies announces the release of its UVM based OCP verification IP. Based on the Open Core Protocol specification 3.0, this VIP is highly configurable and can be used to verify designs with any configuration. This VIP can be used for OCP master/slave IP verification. It can also be used to mimic a processor at the SOC level. The VIP comes with an extensive assertion suite and testsuite to plug all the holes in OCP IP verification.  The Open Core Protocol (OCP), is a protocol for on-chip subsystem communications. It is an openly licensed, core-centric protocol and defines a bus-independent, configurable interface. The

Asiczen Releases HBM Verification IP

Asiczen Technologies announces the release of its UVM based HBM verification IP. Based on the JEDEC standard, this VIP supports both HBM host and device. With configurable timing parameters, memory size, number of channels and pseudo mode support, this VIP equips the user with all he needs to verify a HBM host or memory. High Bandwidth Memory (HBM) is a high-performance RAM interface for 3D-stacked DRAM. It has been adopted by JEDEC as an industry standard in October 2013. HBM achieves higher bandwidth while using less power in a substantially smaller form factor than DDR4. The HBM technology is similar in principle but incompatible